1. Field of the Invention
This invention relates to a structure and fabrication method of a semiconductor device, and more particularly to a structure and fabrication method of a semiconductor device with high bias.
2. Description of Related Art
As the dimension of semiconductor devices is reduced, channel length of transistors is accordingly reduced as well. This makes operation speed faster but the resulting excessively short channel length causes some problems. The induced problems, or phenomena, are called a short channel effect. For example, when a constant bias is applied on the transistor, an electric field (E-field) is obtained on the channel by a formula of "E-field=bias/channel-length". If the channel length is shorter the E-field becomes stronger, and then electrons within the channel gain more energy because electrons are more strongly accelerated by the stronger E-field. As the E-field exceeds a critical quantity, an electrical breakdown then occurs on the transistor. In another case, if the channel length keeps constant but the bias increases, the E-field also increases so that electrical breakdown occurs.
However, it is quite common for current electronic products, such as a digital versatile disk (DVD) or a liquid crystal display (LCD), to be driven by high bias. A circuit device for driving the DVD and the LCD needs a high bias tolerance of about 12-30 volts. In general, a high-bias semiconductor device mainly utilizes an isolating layer and drift region under the isolating layer to increase the distance between an interchangeable source/drain and a gate. So, the high-bias semiconductor device can normally work with a high-bias power source.
FIGS. 1A-1D are cross-sectional views schematically illustrating a fabrication low for a conventional, high-bias semiconductor device. In FIG. 1A, a semiconductor substrate doped with a first type of dopant is provided (not shown). Then, a well 10 doped with a second type of dopant is formed on the substrate. If the first type of dopant is an N-type then the second type of dopant is a P-type, and if the first type of dopant is a P-type then the second type of dopant is an N-type. The P-type dopant is, for example, boron or gallium, and the N-type dopant is, for example, arsenic or phosphorus. Next, a thermal process is performed on the well 10 to form a pad oxide layer 20 over the well 10. A low chemical vapor deposition (LPCVD) process is performed to form a silicon nitride layer 30 over the pad oxide layer 20.
In FIG. 1A and FIG. 1B, a portion of the silicon nitride layer 30 is removed by photolithography and etching to expose the pad oxide layer 20. The silicon nitride layer 30 becomes a silicon nitride 50, on which a photoresist layer 40 remains. An ion implantation is performed to implant the exposed region of the pad oxide layer 20. A drift region 60 then is formed. The drift region 60 includes, for example, the first type of dopant, gallium.
Next, in FIG. 1C, the photoresist layer 40 is removed. A wet oxidation process is performed by using the silicon nitride layer 50 as a mask to form a field oxide layer 70 above the drift region 60. A bird's beak structure, or an acute structure, occurs on each end of the silicon nitride layer 50. The bird's beak structure is due to a high temperature from the wet oxidation process. The high-temperature environment drives the implanted ions inside the drift region 60 into the well 10 and forms the field oxide layer 70 above the drift region 60, where the field oxide layer 70 is not masked by the silicon nitride layer 50. The field oxide layer 70 pushes each end of the silicon nitride layer 50 to form the bird's beak structure.
In FIG. 1C and FIG. 1D, a wet etching process is performed to remove the silicon nitride layer 50 and the pad oxide layer 20 shown in FIG. 1B so that the well 10 is exposed. Then, a dry oxidation process is performed to form a gate oxide layer 80 over the well 10 and the field oxide layer 70. A gate layer 90 including, for example, polysilicon is formed over the gate oxide layer 80 by, for example, deposition. A portion of the gate oxide layer 80 and the gate layer 90 is removed by photolithography and etching, in which a region of the field oxide layer 70 and the well 10 is exposed. Then an ion implantation process with a high density but low energy condition is performed to implant the first-type dopant into the well 10 on the exposed region. The drift region 60, after implantation, becomes a drift region 100 below the exposed region, which is to serve as an interchangeable source/drain region.
The drift region 100 shown in FIG. 1D is a conventional drift region structure, which transversely increases the distance between the interchangeable source/drain region 100 and the gate layer 90 to prevent electrical breakdown. However this conventional method to solve the problem of electrical breakdown must increase device dimension. Furthermore, this method needs a few different dopant densities in the drift region 100 to increase the breakdown threshold voltage, and needs to employ a few photo-masks for forming this conventional drift region structure.